View M58BW016DB80T3T_6738018.PDF datasheet online --- IC-ON-LINE

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1/63 may 2003 m58bw016bt, m58bw016bb m58bw016dt, m58bw016db 16 mbit (512kb x32, boot block, burst) 3v supply flash memories pe4features summary n supply voltage Cv dd = 2.7v to 3.6v for program, erase and read Cv ddq = v ddqin = 2.4v to 3.6v for i/o buffers Cv pp = 12v for fast program (optional) n high performance C access time: 80, 90 and 100ns C 56mhz effective zero wait-state burst read C synchronous burst reads C asynchronous page reads n hardware block protection Cw p pin lock program and erase n software block protection C tuning protection to lock program and erase with 64 bit user programmable pass- word (m58bw016b version only) n optimized for fdi drivers C fast program / erase suspend latency time < 6s C common flash interface n memory blocks C 8 parameters blocks (top or bottom) C 31 main blocks n low power consumption C 5a typical deep power down C 60a typical standby C automatic standby after asynchronous read n electronic signature C manufacturer code: 20h C top device code m58bw016xt: 8836h C bottom device code m58bw016xb: 8835h figure 1. packages bga lbga80 (za) 10 x 8 ball array pqfp80 (t)
m58bw016bt, m58bw016bb, m58bw016dt, m58bw016db 2/63 table of contents summary description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. lbga connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. pqfp connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 block protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 tuning block protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 2. top boot block addresses, m58bw016bt, m58bw016dt . . . . . . . . . . . . . . . . . . . . . . 11 table 3. bottom boot block addresses, m58bw016bb, m58bw016db . . . . . . . . . . . . . . . . . . . 12 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 address inputs (a0-a18). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 data inputs/outputs (dq0-dq31). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 chip enable (e). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 output enable (g). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 output disable (gd). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 write enable (w). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 reset/power-down (rp). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 latch enable (l). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 burst clock (k). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 burst address advance (b). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 valid data ready (r). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 write protect (wp). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 supply voltage (v dd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 output supply voltage (v ddq ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 input supply voltage (v ddqin ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 program/erase supply voltage (v pp ).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 ground (v ss and v ssq ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 bus operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 asynchronous bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 asynchronous bus read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 asynchronous latch controlled bus read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 asynchronous page read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 asynchronous bus write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 asynchronous latch controlled bus write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 output disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 automatic low power.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 power-down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 electronic signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 4. asynchronous bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 table 5. asynchronous read electronic signature operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3/63 m58bw016bt, m58bw016bb, m58bw016dt, m58bw016db synchronous bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 synchronous burst read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 synchronous burst read suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 6. synchronous burst read bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 burst configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 read select bit (m15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 x-latency bits (m14-m11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 y-latency bit (m9). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 valid data ready bit (m8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 burst type bit (m7).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 valid clock edge bit (m6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 wrap burst bit (m3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 burst length bit (m2-m0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 7. burst configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 8. burst type definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 read memory array command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 read electronic signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 read query command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 read status register command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 clear status register command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 block erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 program command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 program/erase suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 program/erase resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 set burst configuration register command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 tuning protection unlock command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 tuning protection program command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 9. commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 10. program, erase times and program erase endurance cycles . . . . . . . . . . . . . . . . . . 27 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 program/erase controller status (bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 erase suspend status (bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 erase status (bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 program status, tuning protection unlock status (bit 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 v pp status (bit 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 program suspend status (bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 block protection status (bit 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 tuning protection status (bit 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 11. status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 12. absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
m58bw016bt, m58bw016bb, m58bw016dt, m58bw016db 4/63 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 13. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 7. ac measurement input output waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 8. ac measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1 table 14. device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 15. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 9. asynchronous bus read ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 16. asynchronous bus read ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 10. asynchronous latch controlled bus read ac waveforms . . . . . . . . . . . . . . . . . . . . . 34 table 17. asynchronous latch controlled bus read ac characteristics . . . . . . . . . . . . . . . . . . . 34 figure 11. asynchronous page read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 18. asynchronous page read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 12. asynchronous write ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 13. asynchronous latch controlled write ac waveform. . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 19. asynchronous write and latch controlled write ac characteristics . . . . . . . . . . . . . . 38 figure 14. synchronous burst read (data valid from n clock rising edge) . . . . . . . . . . . . . . . 39 table 20. synchronous burst read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 15. synchronous burst read (data valid from n clock rising edge) . . . . . . . . . . . . . . . 40 figure 16. synchronous burst read - continuous - valid data ready output . . . . . . . . . . . . . . . 41 figure 17. synchronous burst read - burst address advance. . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 18. reset, power-down and power-up ac waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 21. reset, power-down and power-up ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . 42 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 19. lbga80 10x12mm - 8x10 ball array, 1mm pitch, bottom view package outline . . . . 43 table 22. lbga80 10x12mm - 8x10 ball array, 1mm pitch, package mechanical data . . . . . . . . 43 figure 20. pqfp80 - 80 lead plastic quad flat pack, package outline . . . . . . . . . . . . . . . . . . . . 44 table 23. pqfp80 - 80 lead plastic quad flat pack, package mechanical data. . . . . . . . . . . . . 44 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 24. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 appendix a. common flash interface - cfi. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 25. query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 26. cfi - query address and data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 27. cfi - device voltage and timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 28. device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 29. extended query information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 appendix b. flow charts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 21. program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 22. program suspend & resume flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . 50 figure 23. block erase flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 24. erase suspend & resume flowchart and pseudo code. . . . . . . . . . . . . . . . . . . . . . . 52 figure 25. unlock device and change tuning protection code flowchart . . . . . . . . . . . . . . . . . 53
5/63 m58bw016bt, m58bw016bb, m58bw016dt, m58bw016db figure 26. unlock device and program a tuning protected block flowchart . . . . . . . . . . . . . . . . 54 figure 27. unlock device and erase a tuning protected block flowchart . . . . . . . . . . . . . . . . . . 55 figure 28. power-up sequence to burst the flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 29. command interface and program erase controller flowchart (a) . . . . . . . . . . . . . . . . 57 figure 30. command interface and program erase controller flowchart (b) . . . . . . . . . . . . . . . . 58 figure 31. command interface and program erase controller flowchart (c) . . . . . . . . . . . . . . . . 59 figure 32. command interface and program erase controller flowchart (d) . . . . . . . . . . . . . . . . 60 figure 33. command interface and program erase controller flowchart (e) . . . . . . . . . . . . . . . . 61 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 30. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
m58bw016bt, m58bw016bb, m58bw016dt, m58bw016db 6/63 summary description the m58bw016b/d is a 16mbit non-volatile flash memory that can be erased electrically at the block level and programmed in-system on a double- word basis using a 2.7v to 3.6v v dd supply for the circuit and a v ddq supply down to 2.4v for the in- put and output buffers. optionally a 12v v pp sup- ply can be used to provide fast program and erase for a limited time and number of program/erase cy- cles. the devices support asynchronous (latch con- trolled and page read) and synchronous bus op- erations. the synchronous burst read interface allows a high data transfer rate controlled by the burst clock, k, signal. it is capable of bursting fixed or unlimited lengths of data. the burst type, latency and length are configurable and can be easily adapted to a large variety of system clock frequencies and microprocessors. all writes are asynchronous. on power-up the memory defaults to read mode with an asynchronous bus. the device has a boot block architecture with an array of 8 parameter block of 64kb each and 31 main blocks of 512kb each. the parameter blocks can be located at the top of the address space, m58bw016bt, m58bw016dt or at the bottom, m58bw016bb, m58bw016db. program and erase commands are written to the command interface of the memory. an on-chip program/erase controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are re- quired to update the memory contents. the end of a program or erase operation can be detected and any error conditions identified in the status regis- ter. the command set required to control the memory is consistent with jedec standards. erase can be suspended in order to perform either read or program in any other block and then re- sumed. program can be suspended to read data in any other block and then resumed. each block can be programmed and erased over 100,000 cy- cles. all blocks are protected during power-up. the m58bw016b features four different levels of block protection to avoid unwanted program/erase oper- ations. the wp pin offers an hardware protection on two of the parameter blocks and all of the main blocks. the program and erase commands can be password protected by the tuning protection command. all program or erase operations are blocked when reset, rp, is held low. the m58bw016d offers the same protection features with the exception of the tuning block protection which is disabled in the factory. a reset/power-down mode is entered when the rp input is low. in this mode the power consump- tion is lower than in the normal standby mode, the device is write protected and both the status and the burst configuration registers are cleared. a recovery time is required when the rp input goes high. the memory is offered in pqfp80 (14 x 20mm) and lbga80 (1.0mm pitch) packages and it is supplied with all the bits erased (set to 1).
7/63 m58bw016bt, m58bw016bb, m58bw016dt, m58bw016db figure 2. logic diagram table 1. signal names ai04155 a0-a18 l dq0-dq31 v dd m58bw016dt m58bw016db e v ss rp g gd v ddq w wp r k v pp b v ssq v ddqin m58bw016bt m58bw016bb a0-a18 address inputs dq0-dq7 data input/output, command input dq8-dq15 data input/output, burst configuration register dq16-dq31 data input/output b burst address advance e chip enable g output enable k burst clock l latch enable r valid data ready (open drain output) rp reset/power-down w write enable gd output disable wp write protect v dd supply voltage v ddq power supply for output buffers v ddqin power supply for input buffers only v pp optional supply voltage for fast program and fast erase operations v ss ground v ssq input/output ground nc not connected internally du dont use as internally connected
m58bw016bt, m58bw016bb, m58bw016dt, m58bw016db 8/63 figure 3. lbga connections (top view through package) ai04151b b dq24 dq7 v ssq f v ddq dq26 dq4 v ddq e dq29 v ss dq0 dq3 d a0 du a7 a11 a18 a17 c a1 a4 a5 a8 rp e a13 a16 b a2 a3 a6 v dd v pp v dd a14 a 8 7 6 5 4 3 2 1 dq20 dq18 dq19 dq17 dq11 dq12 dq13 v ddq dq23 dq8 v ddq h g du gd w v ddqin dq16 r g l dq14 dq15 k j a15 v ss a12 a9 a10 nc du du dq31 dq30 dq2 dq28 dq6 dq25 v ssq dq10 dq9 dq21 wp k du dq1 dq27 dq5 nc dq22
9/63 m58bw016bt, m58bw016bb, m58bw016dt, m58bw016db figure 4. pqfp connections (top view through package) ai04152b 12 1 73 m58bw016bt m58bw016bb 53 v ddq dq24 dq25 dq18 dq17 dq16 dq19 dq20 dq21 dq22 dq23 v ddq dq29 dq26 dq30 du dq31 dq28 dq27 a2 a5 a3 a4 a0 a1 a11 v ss a12 a13 a14 a10 gd wp w du g v ss e k l nc b rp v ddq dq7 dq6 dq13 dq14 dq15 dq12 dq11 dq10 dq9 v ssq dq8 dq2 dq5 dq0 nc a18 a16 a17 dq3 dq4 v ssq v ssq a8 a6 a7 v pp v dd a9 a15 dq1 v ddq v ssq r v dd nc v ddqin 24 25 32 40 41 64 65 80 m58bw016dt m58bw016db
m58bw016bt, m58bw016bb, m58bw016dt, m58bw016db 10/63 block protection the m58bw016b features four different levels of block protection. the m58bw016d has the same block protection with the exception of the tuning block protection, which is disabled in the factory. n write protect pin, wp , - when wp is low, v il , all the lockable parameter blocks (two upper (top ) or lower (bottom)) and all the main blocks are protected. when wp is high (v ih ) all the lockable parameter blocks and all the main blocks are unprotected. n reset/power-down pin, rp , - if the device is held in reset mode (rp at v il ), no program or erase operations can be performed on any block. n tuning block protection : m58bw016b features a 64 bit password protection for program and erase operations for a fixed number of blocks after power-up or reset the device is tuning protected. an unlock command is provided to allow program or erase operations in all the blocks. after a device reset the first two kinds of block pro- tection (w p , rp ) can be combined to give a flexi- ble block protection. they do not affect the tuning block protection. when the two protections are disabled, w p and rp at v ih , the blocks locked by the tuning block protection cannot be modified. all blocks are protected during power-up. tuning block protection. the tuning block protection is a software feature to protect certain blocks from program or erase operations. it allows the user to lock program and erase operations with a user definable 64 bit code. it is only available on the m58bw016b version. the code is written once in the tuning protection register and cannot be erased. when shipped the flash memory will have the tuning protection code bits set to 1'. the user can program a 0 in any of the 64 positions. once programmed it is not possible to reset a bit to 1 as the cells cannot be erased. the tuning protection register can be programmed at any moment (after providing the correct code), however once all bits are set to 0 the tuning protection code can no longer be al- tered. the tuning protection code locks the program and erase operations of 2 parameter and 24 main blocks, blocks 0, 1 and 15-38 for the bottom con- figuration and the blocks 0-23, 37 and 38 for the top configuration. the tuning blocks are "locked" if the tuning protec- tion code has not been provided, and unlocked" once the correct code has been provided. the tun- ing blocks are locked after reset or power-up. the tuning protection status can be monitored in the status register. refer to the status register sec- tion. refer to the command interface section for the tuning protection block unlock and tuning pro- tection program commands. see appendix b, fig- ure 25, 26 and 27 for suggested flowcharts for using the tuning block protection commands. for further information on the tuning block protection refer to application note, an1361.
11/63 m58bw016bt, m58bw016bb, m58bw016dt, m58bw016db table 2. top boot block addresses, m58bw016bt, m58bw016dt note: 1. tp = tuning protected block, only available for the m58bw016b. # size (kbit) address range tp (1) 38 64 7f800h-7ffffh yes 37 64 7f000h-7f7ffh yes 36 64 7e800h-7efffh no 35 64 7e000h-7e7ffh no 34 64 7d800h-7dfffh no 33 64 7d000h-7d7ffh no 32 64 7c800h-7cfffh no 31 64 7c000h-7c7ffh no 30 512 78000h-7bfffh no 29 512 74000h-77fffh no 28 512 70000h-73fffh no 27 512 6c000h-6ffffh no 26 512 68000h-6bfffh no 25 512 64000h-67fffh no 24 512 60000h-63fffh no 23 512 5c000h-5ffffh yes 22 512 58000h-5bfffh yes 21 512 54000h-57fffh yes 20 512 50000h-53fffh yes 19 512 4c000h-4ffffh yes 18 512 48000h-4bfffh yes 17 512 44000h-47fffh yes 16 512 40000h-43fffh yes 15 512 3c000h-3ffffh yes 14 512 38000h-3bfffh yes 13 512 34000h-37fffh yes 12 512 30000h-33fffh yes 11 512 2c000h-2ffffh yes 10 512 28000h-2bfffh yes 9 512 24000h-27fffh yes 8 512 20000h-23fffh yes 7 512 1c000h-1ffffh yes 6 512 18000h-1bfffh yes 5 512 14000h-17fffh yes 4 512 10000h-13fffh yes 3 512 0c000h-0ffffh yes 2 512 08000h-0bfffh yes 1 512 04000h-07fffh yes 0 512 00000h-03fffh yes # size (kbit) address range tp (1)
m58bw016bt, m58bw016bb, m58bw016dt, m58bw016db 12/63 table 3. bottom boot block addresses, m58bw016bb, m58bw016db note: 1. tp = tuning protected block, only available for the m58bw016b. # size (kbit) address range tp (1) 38 512 7c000h-7ffffh yes 37 512 78000h-7bfffh yes 36 512 74000h-77fffh yes 35 512 70000h-73fffh yes 34 512 6c000h-6ffffh yes 33 512 68000h-6bfffh yes 32 512 64000h-67fffh yes 31 512 60000h-63fffh yes 30 512 5c000h-5ffffh yes 29 512 58000h-5bfffh yes 28 512 54000h-57fffh yes 27 512 50000h-53fffh yes 26 512 4c000h-4ffffh yes 25 512 48000h-4bfffh yes 24 512 44000h-47fffh yes 23 512 40000h-43fffh yes 22 512 3c000h-3ffffh yes 21 512 38000h-3bfffh yes 20 512 34000h-37fffh yes 19 512 30000h-33fffh yes 18 512 2c000h-2ffffh yes 17 512 28000h-2bfffh yes 16 512 24000h-27fffh yes 15 512 20000h-23fffh yes 14 512 1c000h-1ffffh no 13 512 18000h-1bfffh no 12 512 14000h-17fffh no 11 512 10000h-13fffh no 10 512 0c000h-0ffffh no 9 512 08000h-0bfffh no 8 512 04000h-07fffh no 7 64 03800h-03fffh no 6 64 03000h-037ffh no 5 64 02800h-02fffh no 4 64 02000h-027ffh no 3 64 01800h-01fffh no 2 64 01000h-017ffh no 1 64 00800h-00fffh yes 0 64 00000h-007ffh yes # size (kbit) address range tp (1)
13/63 m58bw016bt, m58bw016bb, m58bw016dt, m58bw016db signal descriptions see figure 2, logic diagram and table 1, signal names, for a brief overview of the signals connect- ed to this device. address inputs (a0-a18). the address inputs are used to select the cells to access in the mem- ory array during bus read operations either to read or to program data to. during bus write oper- ations they control the commands sent to the command interface of the internal state machine. chip enable must be low when selecting the ad- dresses. the address inputs are latched on the rising edge of latch enable l or burst clock k, whichever oc- curs first, in a read operation.the address inputs are latched on the rising edge of chip enable, write enable or latch enable, whichever occurs first in a write operation. the address latch is transparent when latch enable is low, v il . the ad- dress is internally latched in an erase or program operation. data inputs/outputs (dq0-dq31). the data in- puts/outputs output the data stored at the selected address during a bus read operation, or are used to input the data during a program operation. dur- ing bus write operations they represent the com- mands sent to the command interface of the internal state machine. when used to input data or write commands they are latched on the rising edge of write enable or chip enable, whichever occurs first. when chip enable and output enable are both low, v il , and output disable is at v ih, the data bus outputs data from the memory array, the electron- ic signature, the cfi information or the contents of the status register. the data bus is high imped- ance when the device is deselected with chip en- able at v ih , output enable at v ih , output disable at v il or reset/power-down at v il . the status register content is output on dq0-dq7 and dq8- dq31 are at v il . chip enable (e ). the chip enable, e , input acti- vates the memory control logic, input buffers, de- coders and sense amplifiers. chip enable, e , at v ih deselects the memory and reduces the power consumption to the standby level. output enable (g ). the output enable, g , gates the outputs through the data output buffers during a read operation, when output disable gd is at v ih . when output enable g is at v ih , the outputs are high impedance independently of output dis- able. output disable (gd ). the output disable, gd , deactivates the data output buffers. when output disable, gd , is at v ih , the outputs are driven by the output enable. when output disable, gd , is at v il , the outputs are high impedance independent- ly of output enable. the output disable pin must be connected to an external pull-up resistor as there is no internal pull-up resistor to drive the pin. write enable (w ). the write enable, w , input controls writing to the command interface, input address and data latches. both addresses and data can be latched on the rising edge of write en- able (also see latch enable, l ). reset/power-down (rp ). the reset/power- down, rp , is used to apply a hardware reset to the memory. a hardware reset is achieved by holding reset/power-down low, v il , for at least t plph . writing is inhibited to protect data, the command interface and the program/erase controller are re- set. the status register information is cleared and power consumption is reduced to deep power- down level. the device acts as deselected, that is the data outputs are high impedance. after reset/power-down goes high, v ih , the memory will be ready for bus read operations af- ter a delay of t phel or bus write operations after t phwl . if reset/power-down goes low, v il , during a block erase, a program or a tuning protection program the operation is aborted, in a time of t plrh maxi- mum, and data is altered and may be corrupted. during power-up power should be applied simulta- neously to v dd and v ddq(in) with rp held at v il . when the supplies are stable rp is taken to v ih . output enable, g , chip enable, e , and write en- able, w , should be held at v ih during power-up. in an application, it is recommended to associate reset/power-down pin, rp , with the reset signal of the microprocessor. otherwise, if a reset opera- tion occurs while the memory is performing an erase or program operation, the memory may out- put the status register information instead of be- ing initialized to the default asynchronous random read. see table 21 and figure 18, reset, power-down and power-up characteristics, for more details. latch enable (l ). the bus interface can be con- figured to latch the address inputs on the rising edge of latch enable, l , for asynchronous latch enable controlled read or write or synchronous burst read operations. in synchronous burst read operations the address is latched on the ac- tive edge of the clock when latch enable is low, v il . once latched, the addresses may change without affecting the address used by the memory. when latch enable is low, v il , the latch is trans- parent. latch enable, l , can remain at v il for asynchronous random read and write opera- tions. burst clock (k). the burst clock, k, is used to synchronize the memory with the external bus dur-
m58bw016bt, m58bw016bb, m58bw016dt, m58bw016db 14/63 ing synchronous burst read operations. bus sig- nals are latched on the active edge of the clock. the clock can be configured to have an active ris- ing or falling edge. in synchronous burst read mode the address is latched on the first active clock edge when latch enable is low, v il , or on the rising edge of latch enable, whichever occurs first. during asynchronous bus operations the clock is not used. burst address advance (b ). the burst address advance, b , controls the advancing of the address by the internal address counter during synchro- nous burst read operations. burst address advance, b , is only sampled on the active clock edge of the clock when the x-latency time has expired. if burst address advance is low, v il , the internal address counter advances. if burst address advance is high, v ih , the internal address counter does not change; the same data remains on the data inputs/outputs and burst ad- dress advance is not sampled until the y-latency expires. the burst address advance, b , may be tied to v il . valid data ready (r). the valid data ready output, r, is an open drain output that can be used, during synchronous burst read operations, to identify if the memory is ready to output data or not. the valid data ready output can be config- ured to be active on the clock edge of the invalid data read cycle or one cycle before. valid data ready, at v ih , indicates that new data is or will be available. when valid data ready is low, v il , the previous data outputs remain active. in all asynchronous operations, valid data ready is high-impedance. it may be tied to other compo- nents with the same valid data ready signal to create a unique system ready signal. the valid data ready output has an internal pull-up resistor of around 1 m w powered from v ddq , designers should use an external pull-up resistor of the cor- rect value to meet the external timing require- ments for valid data ready going to v ih . write protect (wp ). the write protect, wp , pro- vides protection against program or erase opera- tions. when write protect, wp , is at v il the first two (in the bottom configuration) or last two (in the top configuration) parameter blocks and all main blocks are locked. when write protect wp is at v ih all the blocks can be programmed or erased, if no other protection is used. supply voltage (v dd ). the supply voltage, v dd , is the core power supply. all internal circuits draw their current from the v dd pin, including the pro- gram/erase controller. output supply voltage (v ddq ). the output sup- ply voltage, v ddq , is the output buffer power supply for all operations (read, program and erase) used for dq0-dq31 when used as outputs. input supply voltage (v ddqin ). the input sup- ply voltage, v ddin , is the power supply for all input signal. input signals are: k, b , l , w , gd , g , e , a0- a18 and d0-d31, when used as inputs. program/erase supply voltage (v pp ). the pro- gram/erase supply voltage, v pp , is used for pro- gram and erase operations. the memory normally executes program and erase operations at v pp1 voltage levels. in a manufacturing environment, programming may be speeded up by applying a higher voltage level, v pph , to the v pp pin. the voltage level v pph may be applied for a total of 80 hours over a maximum of 1000 cycles. stressing the device beyond these limits could damage the device. ground (v ss and v ssq ). the ground v ss is the reference for the internal supply voltage v dd . the ground v ssq is the reference for the output and input supplies v ddq, and v ddqin . it is essential to connect v ss and v ssq together. note: a 0.1 m f capacitor should be connected between the supply voltages, v dd , v ddq and v ddin and the grounds, v ss and v ssq to decou- ple the current surges from the power supply. the pcb track widths must be sufficient to car- ry the currents required during all operations of the parts, see table 15, dc characteristics, for maximum current supply requirements. dont use (du). this pin should not be used as it is internally connected. its voltage level can be be- tween v ss and v ddq or leave it unconnected. not connected (nc). this pin is not physically connected to the device.
15/63 m58bw016bt, m58bw016bb, m58bw016dt, m58bw016db bus operations each bus operations that controls the memory is described in this section, see tables 4, 5 and 6 bus operations, for a summary. the bus operation is selected through the burst configuration regis- ter; the bits in this register are described at the end of this section. on power-up or after a hardware reset the mem- ory defaults to asynchronous bus read and asyn- chronous bus write, no other bus operation can be performed until the burst control register has been configured. the electronic signature, cfi or status register will be read in asynchronous mode regardless of the burst control register settings. typically glitches of less than 5ns on chip enable or write enable are ignored by the memory and do not affect bus operations. asynchronous bus operations for asynchronous bus operations refer to table 4 together with the following text. asynchronous bus read. asynchronous bus read operations read from the memory cells, or specific registers (electronic signature, status register, cfi and burst configuration register) in the command interface. a valid bus operation in- volves setting the desired address on the address inputs, applying a low signal, v il , to chip enable and output enable and keeping write enable and output disable high, v ih . the data inputs/out- puts will output the value, see figure 9, asynchro- nous bus read ac waveforms, and table 16, asynchronous bus read ac characteristics, for details of when the output becomes valid. asynchronous read is the default read mode which the device enters on power-up or on return from reset/power-down. asynchronous latch controlled bus read. asynchronous latch controlled bus read opera- tions read from the memory cells or specific regis- ters in the command interface. the address is latched in the memory before the value is output on the data bus, allowing the address to change during the cycle without affecting the address that the memory uses. a valid bus operation involves setting the desired address on the address inputs, setting chip en- able and latch enable low, v il and keeping write enable high, v ih ; the address is latched on the ris- ing edge of latch enable. once latched, the ad- dress inputs can change. set output enable low, v il , to read the data on the data inputs/outputs; see figure 1, asynchronous latch controlled bus read ac waveforms and table 17, asynchro- nous latch controlled bus read ac characteris- tics for details on when the output becomes valid. note that, since the latch enable input is transpar- ent when set low, v il , asynchronous bus read operations can be performed when the memory is configured for asynchronous latch enable bus operations by holding latch enable low, v il throughout the bus operation. asynchronous page read. asynchronous page read operations are used to read from sev- eral addresses within the same memory page. each memory page is 4 double-words and is ad- dressed by the address inputs a0 and a1. data is read internally and stored in the page buff- er. valid bus operations are the same as asyn- chronous bus read operations but with different timings. the first read operation within the page has identical timings, subsequent reads within the same page have much shorter access times. if the page changes then the normal, longer timings ap- ply again. page read does not support latched controlled read. see figure 11, asynchronous page read ac waveforms and table 18, asynchronous page read ac characteristics for details on when the outputs become valid. asynchronous bus write. asynchronous bus write operations write to the command interface in order to send commands to the memory or to latch addresses and input data to program. bus write operations are asynchronous, the clock, k, is dont care during bus write operations. a valid asynchronous bus write operation begins by setting the desired address on the address in- puts, and setting chip enable, write enable and latch enable low, v il , and output enable high, v ih , or output disable low, v il . the address in- puts are latched by the command interface on the rising edge of chip enable or write enable, which- ever occurs first. commands and input data are latched on the rising edge of chip enable, e , or write enable, w , whichever occurs first. output enable must remain high, and output disable low, during the whole asynchronous bus write operation. see figure 12, asynchronous write ac wave- forms, and table 19, asynchronous write and latch controlled write ac characteristics, for de- tails of the timing requirements. asynchronous latch controlled bus write. asynchronous latch controlled bus write opera- tions write to the command interface in order to send commands to the memory or to latch ad- dresses and input data to program. bus write op- erations are asynchronous, the clock, k, is dont care during bus write operations. a valid asynchronous latch controlled bus write operation begins by setting the desired address on
m58bw016bt, m58bw016bb, m58bw016dt, m58bw016db 16/63 the address inputs and pulsing latch enable low, v il . the address inputs are latched by the com- mand interface on the rising edge of latch enable, write enable or chip enable, whichever occurs first. commands and input data are latched on the rising edge of chip enable, e , or write enable, w , whichever occurs first. output enable must remain high, and output disable low, during the whole asynchronous bus write operation. see figure 13, asynchronous latch controlled write ac waveforms, and table 19, asynchro- nous write and latch controlled write ac charac- teristics, for details of the timing requirements. output disable. the data outputs are high im- pedance when the output enable, g , is at v ih or output disable, gd , is at v il . standby. when chip enable is high, v ih , and the program/erase controller is idle, the memory en- ters standby mode, the power consumption is re- duced to the standby level and the data inputs/ outputs pins are placed in the high impedance state regardless of output enable, write enable or output disable inputs. automatic low power. if there is no change in the state of the bus for a short period of time during asynchronous bus read operations the memory enters auto low power mode where the internal supply current is reduced to the auto-standby supply current. the data inputs/outputs will still output data if a bus read operation is in progress. automatic low power is only available in asyn- chronous read modes. power-down. the memory is in power-down when reset/power-down, rp , is at v il . the pow- er consumption is reduced to the power-down lev- el and the outputs are high impedance, independent of the chip enable, e , output enable, g , output disable, gd , or write enable, w, inputs. electronic signature. two codes identifying the manufacturer and the device can be read from the memory allowing programming equipment or ap- plications to automatically match their interface to the characteristics of the memory. the electronic signature is output by giving the read electronic signature command. the manufacturer code is output when all the address inputs are at v il . the device code is output when a1 is at v ih and all the other address pins are at v il . see table 5. issue a read memory array command to return to read mode. table 4. asynchronous bus operations note: x = dont care bus operation step e g gd w rp l a0-a18 dq0-dq31 asynchronous bus read v il v il v ih v ih v ih v il address data output asynchronous latch controlled bus read address latch v il v ih v ih v il v ih v il address high z read v il v il v ih v ih v ih v ih x data output asynchronous page read v il v il v ih v ih v ih x address data output asynchronous bus write v il v ih x v il v ih v il address data input asynchronous latch controlled bus write address latch v il v il v ih v ih v ih v il address high z write v il v ih x v il v ih v ih x data input output disable, g v il v ih v ih v ih v ih x x high z output disable, gd v il v il v il v ih v ih x x high z standby v ih xxx v ih x x high z reset/power-down x x x x v il x x high z
17/63 m58bw016bt, m58bw016bb, m58bw016dt, m58bw016db table 5. asynchronous read electronic signature operation note: 1. x= b or d version of the device. 2. bcr= burst configuration register. synchronous bus operations for synchronous bus operations refer to table 6 together with the following text. synchronous burst read. synchronous burst read operations are used to read from the memo- ry at specific times synchronized to an external ref- erence clock. the burst type, length and latency can be configured. the different configurations for synchronous burst read operations are de- scribed in the burst configuration register sec- tion. refer to figures 5 and 6 for examples of synchronous burst operations. in continuous burst read, one burst read operation can access the entire memory sequentially by keeping the burst address advance b at v il for the appropriate number of clock cycles. at the end of the memory address space the burst read re- starts from the beginning at address 000000h. a valid synchronous burst read operation begins when the burst clock is active and chip enable and latch enable are low, v il . the burst start ad- dress is latched and loaded into the internal burst address counter on the valid burst clock k edge (rising or falling depending on the value of m6) or on the rising edge of latch enable, whichever oc- curs first. after an initial memory latency time, the memory outputs data each clock cycle (or two clock cycles depending on the value of m9). the burst address advance b input controls the memory burst output. the second burst output is on the next clock valid edge after the burst address advance b has been pulled low. valid data ready, r, monitors if the memory burst boundary is exceeded and the burst controller of the microprocessor needs to insert wait states. when valid data ready is low on the active clock edge, no new data is available and the memory does not increment the internal address counter at the active clock edge even if burst address ad- vance, b , is low. valid data ready may be configured (by bit m8 of burst configuration register) to be valid immedi- ately at the valid clock edge or one data cycle be- fore the valid clock edge. synchronous burst read will be suspended if burst address advance, b , goes high, v ih . if output enable is at v il and output disable is at v ih , the last data is still valid. if output enable, g , is at v ih or output disable, gd , is at v il , but the burst address advance, b , is at v il the internal burst address counter is incre- mented at each burst clock k valid edge. the synchronous burst read timing diagrams and ac characteristics are described in the ac and dc parameters section. see figures 14, 15, 16 and 17, and table 20. synchronous burst read suspend. during a synchronous burst read operation it is possible to suspend the operation, freeing the data bus for other higher priority devices. a valid synchronous burst read operation is sus- pended when both output enable and burst ad- dress advance are high, v ih . the burst address advance going high, v ih , stops the burst counter and the output enable going high, v ih , inhibits the data outputs. the synchronous burst read oper- ation can be resumed by setting output enable low. code device e g gd w a18-a0 dq31-dq0 manufacturer all v il v il v ih v ih 00000h 00000020h device m58bw016xt (1) v il v il v ih v ih 00001h 00008836h m58bw016xb (1) v il v il v ih v ih 00001h 00008835h burst configuration register v il v il v ih v ih 00005h bcr (2)
m58bw016bt, m58bw016bb, m58bw016dt, m58bw016db 18/63 table 6. synchronous burst read bus operations note: 1. x = don't care, v il or v ih . 2. m15 = 0, bit m15 is in the burst configuration register. 3. t = transition, see m6 in the burst configuration register for details on the active edge of k. bus operation step e g gd rp k (3) l b a0-a18 dq0-dq31 synchronous burst read address latch v il v ih x v ih t v il x address input read v il v il v ih v ih t v ih v il data output read suspend v il v ih x v ih x v ih v ih high z read resume v il v il v ih v ih t v ih v il data output burst address advance v il v ih x v ih t v ih v il high z read abort, e v ih xx v ih x x x high z read abort, rp xxx v il x x x high z
19/63 m58bw016bt, m58bw016bb, m58bw016dt, m58bw016db burst configuration register the burst configuration register is used to config- ure the type of bus access that the memory will perform. the burst configuration register is set through the command interface and will retain its informa- tion until it is re-configured, the device is reset, or the device goes into reset/power-down mode. the burst configuration register bits are de- scribed in table 7. they specify the selection of the burst length, burst type, burst x and y laten- cies and the read operation. refer to figures 5 and 6 for examples of synchronous burst configu- rations. read select bit (m15). the read select bit, m15, is used to switch between asynchronous and synchronous bus read operations. when the read select bit is set to 1, bus read operations are asynchronous; when the read select but is set to 0, bus read operations are synchronous. on reset or power-up the read select bit is set to1 for asynchronous accesses. x-latency bits (m14-m11). the x-latency bits are used during synchronous bus read opera- tions to set the number of clock cycles between the address being latched and the first data be- coming available. for correct operation the x-la- tency bits can only assume the values in table 7, burst configuration register. the x-latency bits should also be selected in conjunction with table , burst performance to ensure valid settings. y-latency bit (m9). the y-latency bit is used during synchronous bus read operations to set the number of clock cycles between consecutive reads. the y-latency value depends on both the x-latency value and the setting in m9. when the y-latency is 1 the data changes each clock cycle; when the y-latency is 2 the data changes every second clock cycle. see table 7, burst configuration register and table , burst performance, for valid combinations of the y-la- tency, the x-latency and the clock frequency. valid data ready bit (m8). the valid data ready bit controls the timing of the valid data ready output pin, r. when the valid data ready bit is 0 the valid data ready output pin is driven low for the active clock edge when invalid data is output on the bus. when the valid data ready bit is 1 the valid data ready output pin is driven low one clock cycle prior to invalid data being output on the bus. burst type bit (m7). the burst type bit is used to configure the sequence of addresses read as sequential or interleaved. when the burst type bit is 0 the memory outputs from interleaved ad- dresses; when the burst type bit is 1 the memory outputs from sequential addresses. see tables 8, burst type definition, for the sequence of ad- dresses output from a given starting address in each mode. valid clock edge bit (m6). the valid clock edge bit, m6, is used to configure the active edge of the clock, k, during synchronous burst read operations. when the valid clock edge bit is 0 the falling edge of the clock is the active edge; when the valid clock edge bit is 1 the rising edge of the clock is active. wrap burst bit (m3). the burst reads can be confined inside the 4 or 8 double-word boundary (wrap) or overcome the boundary (no wrap). the wrap burst bit is used to select between wrap and no wrap. when the wrap burst bit is set to 0 the burst read wraps; when it is set to 1 the burst read does not wrap. burst length bit (m2-m0). the burst length bits set the maximum number of double-words that can be output during a synchronous burst read operation before the address wraps. burst lengths of 4 or 8 are available for both the sequential and interleaved burst types, and a continuous burst is available for the sequential type. table 7, burst configuration register gives the valid combinations of the burst length bits that the memory accepts; table 8, burst type definition, gives the sequence of addresses output from a given starting address for each length. if either a continuous or a no wrap burst read has been initiated the device will output data syn- chronously. depending on the starting address, the device activates the valid data ready output to indicate that a delay is necessary before the data is output. if the starting address is aligned to an 8 double word boundary, the continuous burst mode will run without activating the valid data ready output. if the starting address is not aligned to an 8 double word boundary, valid data ready is activated to indicate that the device needs an in- ternal delay to read the successive words in the ar- ray. m10, m5 and m4 are reserved for future use.
m58bw016bt, m58bw016bb, m58bw016dt, m58bw016db 20/63 table 7. burst configuration register note: 1. 4 - 2 - 2 - 2 is not allowed. 2. x latencies can be calculated as: (t avqv C t llkh + t qvkh ) + t system margin < (x -1) t k. (x is an integer number from 4 to 8 and t k is the clock period). 3. y latencies can be calculated as: t khqv + t system margin + t qvkh < y t k. 4. t system margin is the time margin required for the calculation. bit description value description m15 read select 0 synchronous burst read 1 asynchronous read (default at power-on) m14 reserved m13-m11 x-latency (2) 001 reserved 010 4, 4-1-1-1 (1) 011 5, 5-1-1-1, 5-2-2-2 100 6, 6-1-1-1, 6-2-2-2 101 7, 7-1-1-1, 7-2-2-2 110 8, 8-1-1-1, 8-2-2-2 m10 reserved m9 y-latency (3) 0 one burst clock cycle 1 two burst clock cycles m8 valid data ready 0 r valid low during valid burst clock edge 1 r valid low one data cycle before valid burst clock edge m7 burst type 0 interleaved 1 sequential m6 valid clock edge 0 falling burst clock edge 1 rising burst clock edge m5-m4 reserved m3 wrapping 0 wrap 1 no wrap m2-m0 burst length 001 4 double-words 010 8 double-words 111 continuous
21/63 m58bw016bt, m58bw016bb, m58bw016dt, m58bw016db table 8. burst type definition m 3 starting address x4 sequential x4 interleaved x8 sequential x8 interleaved continuous 0 0 0-1-2-3 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7-8-9-10.. 0 1 1-2-3-0 1-0-3-2 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 1-2-3-4-5-6-7-8-9-10-11.. 0 2 2-3-0-1 2-3-0-1 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 2-3-4-5-6-7-8-9-10-11-12.. 0 3 3-0-1-2 3-2-1-0 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 3-4-5-6-7-8-9-10-11-12-13.. 0 4 C C 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 4-5-6-7-8-9-10-11-2-13-14.. 0 5 C C 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 5-6-7-8-9-10-11-12-13-14.. 0 6 C C 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 6-7-8-9-10-11-12-13-14-15.. 0 7 C C 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 7-8-9-10-11-12-13-14-15-16.. 0 8 C C C C 8-9-10-11-12-13-14-15-16-17.. 1 0 0-1-2-3 C 0-1-2-3-4-5-6-7 C 0-1-2-3-4-5-6-7-8-9-10.. 1 1 1-2-3-4 C 1-2-3-4-5-6-7-8 C 1-2-3-4-5-6-7-8-9-10-11.. 1 2 2-3-4-5 C 2-3-4-5-6-7-8-9 C 2-3-4-5-6-7-8-9-10-11-12.. 1 3 3-4-5-6 C 3-4-5-6-7-8-9-10 C 3-4-5-6-7-8-9-10-11-12-13.. 1 4 4-5-6-7 C 4-5-6-7-8-9-10- 11 C 4-5-6-7-8-9-10-11-12-13-14.. 1 5 5-6-7-8 C 5-6-7-8-9-10-11- 12 C 5-6-7-8-9-10-11-12-13-14.. 1 6 6-7-8-9 C 6-7-8-9-10-11- 12-13 C 6-7-8-9-10-11-12-13-14-15.. 1 7 7-8-9-10 C 7-8-9-10-11-12- 13-14 C 7-8-9-10-11-12-13-14-15-16.. 1 8 8-9-10-11 C 8-9-10-11-12-13- 14-15 C 8-9-10-11-12-13-14-15-16-17..
m58bw016bt, m58bw016bb, m58bw016dt, m58bw016db 22/63 figure 5. example burst configuration x-1-1-1 figure 6. example burst configuration x-2-2-2 ai03841 k dq l add valid dq dq dq dq 4-1-1-1 5-1-1-1 6-1-1-1 7-1-1-1 8-1-1-1 0123456789 valid valid valid valid valid valid valid valid valid valid valid valid valid valid valid valid valid valid valid valid ai04406b k l add dq valid dq dq dq 5-2-2-2 6-2-2-2 7-2-2-2 8-2-2-2 0123456789 valid valid valid valid valid valid valid valid nv nv nv nv nv nv nv nv nv nv nv=not valid
23/63 m58bw016bt, m58bw016bb, m58bw016dt, m58bw016db command interface all bus write operations to the memory are inter- preted by the command interface. commands consist of one or more sequential bus write oper- ations. the commands are summarized in table 9, commands. refer to table 9 in conjunction with the text descriptions below. read memory array command the read memory array command returns the memory to read mode. one bus write cycle is re- quired to issue the read memory array command and return the memory to read mode. subse- quent read operations will output the addressed memory array data. once the command is issued the memory remains in read mode until another command is issued. from read mode bus read commands will access the memory array. read electronic signature command the read electronic signature command is used to read the manufacturer code, the device code or the burst configuration register. one bus write cycle is required to issue the read electronic sig- nature command. once the command is issued subsequent bus read operations, depending on the address specified, read the manufacturer code, the device code or the burst configuration register until another command is issued; see ta- ble 5, read electronic signature. read query command. the read query command is used to read data from the common flash interface (cfi) memory area. one bus write cycle is required to issue the read query command. once the command is is- sued subsequent bus read operations, depend- ing on the address specified, read from the common flash interface memory area. see ap- pendix a, tables 25, 26, 27, 28 and 29 for details on the information contained in the common flash interface (cfi) memory area. read status register command the read status register command is used to read the status register. one bus write cycle is required to issue the read status register com- mand. once the command is issued subsequent bus read operations read the status register un- til another command is issued. the status register information is present on the output data bus (dq1-dq7) when chip enable e and output enable g are at v il and output dis- able is at v ih . an interactive update of the status register bits is possible by toggling output enable or output dis- able. it is also possible during a program or erase operation, by disactivating the device with chip enable at v ih and then reactivating it with chip en- able and output enable at v il and output disable at v ih . the content of the status register may also be read at the completion of a program, erase or suspend operation. during a block erase, pro- gram, tuning protection program or tuning pro- tection unlock command, dq7 indicates the program/erase controller status. it is valid until the operation is completed or suspended. see the section on the status register and table 11 for details on the definitions of the status reg- ister bits clear status register command the clear status register command can be used to reset bits 1, 3, 4 and 5 in the status register to 0. one bus write is required to issue the clear status register command. once the command is issued the memory returns to its previous mode, subsequent bus read operations continue to out- put the same data. the bits in the status register are sticky and do not automatically return to 0 when a new pro- gram, erase, block protect or block unprotect command is issued. if any error occurs then it is essential to clear any error bits in the status reg- ister by issuing the clear status register com- mand before attempting a new program, erase or resume command. block erase command the block erase command can be used to erase a block. it sets all of the bits in the block to 1. all previous data in the block is lost. if the block is pro- tected then the erase operation will abort, the data in the block will not be changed and the status register will output the error. two bus write operations are required to issue the command; the first write cycle sets up the block erase command, the second write cycle confirms the block erase command and latches the block address in the internal state machine and starts the program/erase controller. the sequence is aborted if the confirm command is not given and the device will output the status register data with bits 4 and 5 set to '1'. once the command is issued subsequent bus read operations read the status register. see the section on the status register for details on the definitions of the status register bits. during the erase operation the memory will only accept the read status register command and the program/ erase suspend command. all other commands will be ignored. the command can be executed using either v dd (for a normal erase operation) or v pp (for a fast erase operation). if v pp is in the v pph range when
m58bw016bt, m58bw016bb, m58bw016dt, m58bw016db 24/63 the command is issued then a fast erase operation will be executed, otherwise the operation will use v dd . if v pp goes below the v pp lockout voltage, v pplk , during a fast erase the operation aborts, the status register v pp status bit is set to 1 and the command must be re-issued. typical erase times are given in table 10. see appendix b, figure 23, block erase flowchart and pseudo code, for a suggested flowchart on using the block erase command. program command. the program command is used to program the memory array. two bus write operations are re- quired to issue the command; the first write cycle sets up the program command, the second write cycle latches the address and data to be pro- grammed in the internal state machine and starts the program/erase controller. a program opera- tion can be aborted by writing ffffffffh to any address after the program set-up command has been given. once the command is issued subsequent bus read operations read the status register. see the section on the status register for details on the definitions of the status register bits. during the program operation the memory will only accept the read status register command and the pro- gram/erase suspend command. all other com- mands will be ignored. if reset/power-down, rp , falls to v il during pro- gramming the operation will be aborted. the command can be executed using either v dd (for a normal program operation) or v pp (for a fast program operation). if v pp is in the v pph range when the command is issued then a fast program operation will be executed, otherwise the opera- tion will use v dd . if v pp goes below the v pp lock- out voltage, v pplk , during a fast program the operation aborts and the status register v pp sta- tus bit is set to 1. as data integrity cannot be guar- anteed when the program operation is aborted, the memory block must be erased and repro- grammed. see appendix b, figure 21, program flowchart and pseudo code, for a suggested flowchart on using the program command. program/erase suspend command the program/erase suspend comm and is used to pause a program or erase operation. the com- mand will only be accepted during a program or erase operation. it can be issued at any time dur- ing a program or erase operation. the command is ignored if the device is already in suspend mode. one bus write cycle is required to issue the pro- gram/erase suspend command and pause the program/erase controller. once the command is issued it is necessary to poll the program/erase controller status bit (bit 7) to find out when the program/erase controller has paused; no other commands will be accepted until the program/ erase controller has paused. after the program/ erase controller has paused, the memory will con- tinue to output the status register until another command is issued. during the polling period between issuing the pro- gram/erase suspend command and the program/ erase controller pausing it is possible for the op- eration to complete. once the program/erase controller status bit (bit 7) indicates that the pro- gram/erase controller is no longer active, the pro- gram suspend status bit (bit 2) or the erase suspend status bit (bit 6) can be used to deter- mine if the operation has completed or is suspend- ed. for timing on the delay between issuing the program/erase suspend command and the pro- gram/erase controller pausing see table 10. during program/erase suspend the read memo- ry array, read status register, read electronic signature, read query and program/erase re- sume commands will be accepted by the com- mand interface. additionally, if the suspended operation was erase then the program and the program suspend commands will also be accept- ed. when a program operation is completed inside a block erase suspend the read memory array command must be issued to reset the device in read mode, then the erase resume command can be issued to complete the whole sequence. only the blocks not being erased may be read or programmed correctly. see appendix b, figure 22, program suspend & resume flowchart and pseudo code, and figure 24, erase suspend & resume flowchart and pseudo code, for suggested flowcharts on using the program/erase suspend command. program/erase resume command the program/erase resume command can be used to restart the program/erase controller after a program/erase suspend operation has paused it. one bus write cycle is required to issue the pro- gram/erase resume command. see appendix b, figure 22, program suspend & resume flowchart and pseudo code, and figure 24, erase suspend & resume flowchart and pseudo code, for suggested flowcharts on using the program/erase resume command. set burst configuration register command. the set burst configuration register command is used to write a new value to the burst configura- tion control register which defines the burst length, type, x and y latencies, synchronous/
25/63 m58bw016bt, m58bw016bb, m58bw016dt, m58bw016db asynchronous read mode and the valid clock edge configuration. two bus write cycles are required to issue the set burst configuration register command. the first cycle writes the setup command and the address corresponding to the set burst configuration reg- ister content. the second cycle writes the burst configuration register data and the confirm com- mand. once the command is issued the memory returns to read mode as if a read memory array command had been issued. the value for the burst configuration register is always presented on a0-a15. m0 is on a0, m1 on a1, etc.; the other address bits are ignored. tuning protection unlock command the tuning protection unlock command unlocks the tuning protected blocks by writing the 64bit tuning protection code (m58bw016b only). after a reset or power-up the blocks are locked and so a tuning protection unlock command must be is- sued to allow program or erase operations on tun- ing protected block or to program a new tuning protection code. read operations output the sta- tus register content after the unlock operation has started. the tuning protection code is composed of 64 bits, but the data bus is 32 bits wide so four (2 x 2) write cycles are required to unlock the device. n the first write cycle issues the tuning protection unlock setup command (0x78). n the second write cycle inputs the first 32 bits of the tuning protection code on the data bus, at address 0x00000. bit 7 of the status register should now be checked to verify that the device has successfully stored the first part of the code in the internal reg- ister. if b7 = 1, the device is ready to accept the second part of the code. this does not mean that the first 32 bits match the tuning protection code, simply that it was correctly stored for the compar- ing. if b7 = 0, the user must wait for this bit setting (refer to write cycle ac timings). n the third write cycle re-issues the tuning protection unlock setup command (0x78). n the fourth write cycle inputs the second 32 bits of the code at address 0x00001. bit 7 of the status register should again be checked to verify that the device has successfully stored the second part of the code. when the de- vice is ready (b7 = 1), the tuning protection status can be monitored on status register bit0. if b0 = 0 the device is locked; b0 = 1 the device is un- locked. if the device is still locked a read memory array command must be issued before re-issuing the tuning protection unlock command. device locked means that the 64 bit password is wrong. if the unlock operation is attempted using a wrong code on an already unlocked device, the device becomes locked. status register bit 4 is set to '1' if there has been a verify failure. unlocking aborts if v pp drops out of the allowed range or rp goes to v il . once the device is successfully unlocked, a read memory array command must be issued to return the memory to read mode before issuing any other commands. the user can then program or erase all blocks, depending on wp status and v pp level. at this point, it is also possible to configure a new protection code. to write a new protection code into the device tuning register, the user must per- form the tuning protection program sequence. the device can be re-locked with a reset or power- down. see appendix b, figure 25, 26 and 27 for suggest- ed flowcharts for using the tuning protection un- lock command. tuning protection program command. the tuning protection program command is used to program a new tuning protection code which can be configured by the designer of the applica- tion (m58bw016b only). the device should be un- locked by the tuning protection unlock command before issuing the tuning protection program command. read operations output the status register con- tent after the program operation has started. the tuning protection code is composed of 64 bits, but the data bus is 32 bits wide so four (2 x 2) write cycles are required to program the code. n the first write cycle issues the tuning protection program setup command (0x48). n the second write cycle inputs the first 32 bits of the new tuning protection code on the data bus, at address 0x00000. bit 7 of the status register should now be checked to verify that the device has successfully stored the first part of the code in the internal reg- ister. if b7 = 1, the device is ready to accept the second part of the code. if b7 = 0, the user must wait for this bit setting (refer to write cycle ac tim- ings). n the third write cycle re-issues the tuning protection program setup command (0x48). n the fourth write cycle inputs the second 32 bits of the new code at address 0x00001. bit 7 of the status register should again be checked to verify that the device has successfully stored the second part of the code. when the de- vice is ready (b7 = 1). after completion status
m58bw016bt, m58bw016bb, m58bw016dt, m58bw016db 26/63 register bit 4 is set to '1' if there has been a pro- gram failure. programming aborts if v pp drops out of the al- lowed range or rp goes to v il . a read memory array command must be issued to return the memory to read mode before issuing any other commands. once the code has been changed a device reset or power-down will make the protection active with the new code. see appendix b, figure 25, 26 and 27 for suggest- ed flowcharts for using the tuning protection pro- gram command. table 9. commands note: 1. x dont care; ra read address, rd read data, id device code, srd status register data, pa program address; pd program data, qa query address, qd query data, ba any address in the block, bcr burst configuration register value, tpa = tuning protection address, tpc = tuning protection code. 2. cycles 1 and 2 input the first 32 bits of the code, cycles 3 and 4 the second 32 bits of the code. command cycles bus operations 1st cycle 2nd cycle 3rd cycle 4th cycle op. addr. data op. addr. data op. addr. data op. addr. data read memory array 3 2 write x ffh read ra rd read electronic signature (manufacturer code) 3 2 write x 90h read 00000h 20h read electronic signature (device code) 3 2 write x 90h read 00001h idh read electronic signature (burst configuration register) 3 2 write x 90h read 00005h bcrh read status register 2 write x 70h read x srdh read query 3 2 write x 98h read qah qdh clear status register 1 write x 50h block erase 2 write x 20h write bah d0h program 2 write x 40h 10h write pa pd program/erase suspend 1 write x b0h program/erase resume 1 write x d0h set burst configuration register 2 write x 60h write bcrh 03h tuning protection (2) program 4 write x 48h write tpah tpch write x 48h write tpah tpch tuning protection unlock (2) 4 write x 78h write tpah tpch write x 78h write tpah tpch
27/63 m58bw016bt, m58bw016bb, m58bw016dt, m58bw016db table 10. program, erase times and program erase endurance cycles note: t a = C40 to 125c, v dd = 2.7v to 3.6v, v ddq = 2.4v to v dd parameters m58bw016b/d unit min typ max v pp = v dd v pp = 12v v pp = v dd v pp = 12v parameter block (64kb) program 0.030 0.016 0.060 0.032 s main block (512kb) program 0.23 0.13 0.46 0.26 s parameter block erase 0.8 0.64 1.8 1.5 s main block erase 1.5 0.9 3 1.8 s program suspend latency time 3 10 s erase suspend latency time 10 30 s program/erase cycles (per block) 100,000 cycles
m58bw016bt, m58bw016bb, m58bw016dt, m58bw016db 28/63 status register the status register provides information on the current or previous program, erase, block protect or tuning protection operation. the various bits in the status register convey information and errors on the operation. they are output on dq7-dq0. to read the status register the read status reg- ister command can be issued. the status register is automatically read after program, erase, block protect, program/erase resume commands. the status register can be read from any address. the contents of the status register can be updat- ed during an erase or program operation by tog- gling the output enable or output disable pins or by dis-activating (chip enable, v ih ) and then reac- tivating (chip enable and output enable, v il , and output disable, v ih .) the device. the status register bits are summarized in table 11, status register bits. refer to table 11 in con- junction with the following text descriptions. program/erase controller status (bit 7) the program/erase controller status bit indicates whether the program/erase controller is active or inactive. when the program/erase controller sta- tus bit is set to 0, the program/erase controller is active; when bit7 is set to 1, the program/erase controller is inactive. the program/erase controller status is set to 0 immediately after a program/erase suspend com- mand is issued until the program/erase controller pauses. after the program/erase controller paus- es the bit is set to 1. during program and erase operations the pro- gram/erase controller status bit can be polled to find the end of the operation. the other bits in the status register should not be tested until the pro- gram/erase controller completes the operation and the bit is set to 1. after the program/erase controller completes its operation the erase status (bit5), program status and tuning protection unlock status (bit4) bits should be tested for errors. erase suspend status (bit 6) the erase suspend status bit indicates that an erase operation has been suspended and is wait- ing to be resumed. the erase suspend status should only be considered valid when the pro- gram/erase controller status bit is set to 1 (pro- gram/erase controller inactive); after a program/ erase suspend command is issued the memory may still complete the operation rather than enter- ing the suspend mode. when the erase suspend status bit is set to 0, the program/erase controller is active or has com- pleted its operation; when the bit is set to 1, a pro- gram/erase suspend command has been issued and the memory is waiting for a program/erase resume command. when a program/erase resume command is is- sued the erase suspend status bit returns to 0. erase status (bit 5) the erase status bit can be used to identify if the memory has failed to verify that the block has erased correctly. the erase status bit should be read once the program/erase controller status bit is high (program/erase controller inactive). when the erase status bit is set to 0, the memory has successfully verified that the block has erased correctly. when the erase status bit is set to 1, the program/erase controller has applied the maximum number of pulses to the block and still failed to verify that the block has erased correctly. once set to 1, the erase status bit can only be re- set to 0 by a clear status register command or a hardware reset. if set to 1 it should be reset be- fore a new program or erase command is issued, otherwise the new command will appear to fail. program status, tuning protection unlock status (bit 4) the program status and tuning protection unlock status bit is used to identify a program failure or a tuning protection code verify failure. bit4 should be read once the program/erase controller status bit is high (program/erase controller inactive). when bit4 is set to 0 the memory has successful- ly verified that the device has programmed cor- rectly or that the correct tuning protection code has been written. when bit4 is set to 1 the device has failed to verify that the data has been pro- grammed correctly or that the correct tuning pro- tection code has been written. once set to 1, the program status bit can only be reset to 0 by a clear status register command or a hardware reset. if set to 1 it should be reset be- fore a new program or erase command is issued, otherwise the new command will appear to fail. v pp status (bit 3) the v pp status bit can be used to identify an in- valid voltage on the v pp pin during fast program and erase operations. the v pp pin is only sampled at the beginning of a program or erase operation. indeterminate results can occur if v pp becomes in- valid during a fast program or erase operation. when the v pp status bit is set to 0, the voltage on the v pp pin was sampled at a valid voltage; when the v pp status bit is set to 1, the v pp pin has a voltage that is below the v pp lockout voltage, v p- plk . once set to 1, the v pp status bit can only be reset to 0 by a clear status register command or a hardware reset. if set to 1 it should be reset be-
29/63 m58bw016bt, m58bw016bb, m58bw016dt, m58bw016db fore a new program or erase command is issued, otherwise the new command will appear to fail. program suspend status (bit 2) the program suspend status bit indicates that a program operation has been suspended and is waiting to be resumed. the program suspend status should only be considered valid when the program/erase controller status bit is set to 1 (program/erase controller inactive); after a pro- gram/erase suspend command is issued the memory may still complete the operation rather than entering the suspend mode. when the program suspend status bit is set to 0, the program/erase controller is active or has com- pleted its operation; when the bit is set to 1, a pro- gram/erase suspend command has been issued and the memory is waiting for a program/erase resume command. when a program/erase resume command is is- sued the program suspend status bit returns to 0. block protection status (bit 1) the block protection status bit can be used to identify if a program or erase operation has tried to modify the contents of a protected block. when the block protection status bit is set to 0, no program or erase operations have been at- tempted to protected blocks since the last clear status register command or hardware reset; when the block protection status bit is set to 1, a program or erase operation has been attempted on a protected block. once set to 1, the block protection status bit can only be reset low by a clear status register com- mand or a hardware reset. if set to 1 it should be reset before a new program or erase command is issued, otherwise the new command will appear to fail. tuning protection status (bit 0) the tuning protection status bit indicates if the device is locked (tuning protection is enabled) or unlocked (tuning protection is disabled). when the tuning protection status bit is set to 0 the device is locked, when it is set to 1 the device is unlocked. after a reset or power-up the device is locked and so bit0 is set to 0. the tuning protection status bit is set to 1 for the m58bw016d version. table 11. status register bits note: 1. for the m58bw016d version the tuning protection status bit is always set to 1. bit name logic level definition 7 program/erase controller status 1 ready 0 busy 6 erase suspend status 1 suspended 0 in progress or completed 5 erase status 1 erase error 0 erase success 4 program status, tuning protection unlock status 1 program error 0 program success 3 v pp status 1 v pp invalid, abort 0 v pp ok 2 program suspend status 1 suspended 0 in progress or completed 1 erase/program in a protected block 1 program/erase on protected block, abort 0 no operations to protected sectors 0 tuning protection status 1 tuning protection disabled (1) 0 tuning protection enabled
m58bw016bt, m58bw016bb, m58bw016dt, m58bw016db 30/63 maximum rating stressing the device above the ratings listed in ta- ble 12, absolute maximum ratings, may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicat- ed in the operating sections of this specification is not implied. exposure to absolute maximum rat- ing conditions for extended periods may affect de- vice reliability. refer also to the stmicroelectronics sure program and other rel- evant quality documents. table 12. absolute maximum ratings note: cumulative time at a high voltage level of 13.5v should not exceed 80 hours on v pp pin. symbol parameter value unit min max t bias temperature under bias C40 125 c t stg storage temperature C55 155 c v io input or output voltage C0.6 v ddq +0.6 v ddqin +0.6 v v dd , v ddq, v ddqin supply voltage C0.6 4.2 v v pp program voltage C0.6 13.5 (1) v
31/63 m58bw016bt, m58bw016bb, m58bw016dt, m58bw016db dc and ac parameters this section summarizes the operating and mea- surement conditions, and the dc and ac charac- teristics of the device. the parameters in the dc and ac characteristics tables that follow, are de- rived from tests performed under the measure- ment conditions summarized in table 13, operating and ac measurement conditions. de- signers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. table 13. operating and ac measurement conditions figure 7. ac measurement input output waveform note: v dd = v ddq . figure 8. ac measurement load circuit table 14. device capacitance note: 1. t a = 25c, f = 1 mhz 2. sampled only, not 100% tested. parameter value units min max supply voltage (v dd ) 2.7 3.6 v input/output supply voltage (v ddq ) 2.4 v dd v ambient temperature (t a ) grade 6 C40 90 c grade 3 C40 125 c load capacitance (c l ) 60 pf clock rise and fall times 4 ns input rise and fall times 4 ns input pulses voltages 0 to v ddq v input and output timing ref. voltages v ddq /2 v ai04153 v ddq v ddqin 0v v ddq /2 v ddqin /2 ai04154 1.3v out c l c l includes jig capacitance 3.3k w 1n914 device under test symbol parameter test condition typ max unit c in input capacitance v in = 0v 68pf c out output capacitance v out = 0v 812pf
m58bw016bt, m58bw016bb, m58bw016dt, m58bw016db 32/63 table 15. dc characteristics symbol parameter test condition min max unit i li input leakage current 0v v in v ddq 1 a i lo output leakage current 0v v out v ddq 5 a i dd supply current (random read) e = v il , g = v ih , f add = 6mhz 20 ma i ddb supply current (burst read) e = v il , g = v ih , f clock = 56mhz 30 ma i dd1 supply current (standby) e = rp = v dd 0.2v 60 a supply current (auto low-power) e = v ss 0.2v, rp = v dd 0.2v 60 a i dd2 supply current (reset/power-down) rp = v ss 0.2v 60 a i dd3 supply current (program or erase, set lock bit, erase lock bit) program, block erase in progress 30 ma i dd4 supply current (erase/program suspend) e = v ih 40 a i pp program current (read or standby) v pp 3 v pp1 30 a i pp1 program current (read or standby) v pp v pp1 30 a i pp2 program current (power-down) rp = v il 5 a i pp3 program current (program) program in progress v pp = v pp1 200 a v pp = v pph 20 ma i pp4 program current (erase) erase in progress v pp = v pp1 200 a v pp = v pph 20 ma v il input low voltage C0.5 0.2v ddqin v v ih input high voltage (for dq lines) 0.8v ddqin v ddq +0.3 v v ih input high voltage (for input only lines) 0.8v ddqin 3.6 v v ol output low voltage i ol = 100a 0.1 v v oh output high voltage cmos i oh = C100a v ddq C0.1 v v pp1 program voltage (program or erase operations) 2.7 3.6 v v pph program voltage (program or erase operations) 11.4 12.6 v v lko v dd supply voltage (erase and program lockout) 2.2 v v pplk v pp supply voltage (erase and program lockout) 11.4 v
33/63 m58bw016bt, m58bw016bb, m58bw016dt, m58bw016db figure 9. asynchronous bus read ac waveforms table 16. asynchronous bus read ac characteristics. note: 1. output enable g may be delayed up to t elqv - t glqv after the falling edge of chip enable e without increasing t elqv . symbol parameter test condition m58bw016 unit 80 90 100 t avav address valid to address valid e = v il , g = v il min 80 90 100 ns t av qv address valid to output valid e = v il , g = v il max 80 90 100 ns t axqx address transition to output transition e = v il , g = v il min 0 0 0 ns t ehlx chip enable high to latch enable transition min 0 0 0 ns t ehqx chip enable high to output transition g = v il min 0 0 0 ns t ehqz chip enable high to output hi-z g = v il max 20 20 20 ns t elqv (1) chip enable low to output valid g = v il max 80 90 100 ns t elqx chip enable low to output transition g = v il min 0 0 0 ns t ghqx output enable high to output transition e = v il min 0 0 0 ns t ghqz output enable high to output hi-z e = v il max 15 15 15 ns t glqv output enable low to output valid e = v il max 25 25 25 ns t glqx output enable to output transition e = v il min 0 0 0 ns t llel latch enable low to chip enable low min 0 0 0 ns ai0440 c e g l a0-a18 dq0-dq31 valid tllel taxqx telqx telqv tavqv tglqx tglqv tehqx tehqz tghqx tghqz see also page read output tehlx tavav gd ai04407c e g l a0-a18 dq0-dq31 valid tllel taxqx telqx telqv tavqv tglqx tglqv tehqx tehqz tghqx tghqz see also page read output tehlx tavav gd
m58bw016bt, m58bw016bb, m58bw016dt, m58bw016db 34/63 figure 10. asynchronous latch controlled bus read ac waveforms table 17. asynchronous latch controlled bus read ac characteristics symbol parameter test condition m58bw016 unit 80 90 100 t avl l address valid to latch enable low e = v il min 0 0 0 ns t ehlx chip enable high to latch enable transition min 0 0 0 ns t ehqx chip enable high to output transition g = v il min 0 0 0 ns t ehqz chip enable high to output hi-z g = v il max 20 20 20 ns t elll chip enable low to latch enable low min 0 0 0 ns t ghqx output enable high to output transition e = v il min 0 0 0 ns t ghqz output enable high to output hi-z e = v il max 15 15 15 ns t glqv output enable low to output valid e = v il max 25 25 25 ns t glqx output enable low to output transition e = v il min 0 0 0 ns t lhax latch enable high to address transition e = v il min 5 5 5 ns t lhll latch enable high to latch enable low min 10 10 10 ns t lllh latch enable low to latch enable high e = v il min 10 10 10 ns t llqv latch enable low to output valid e = v il , g = v il max 80 90 100 ns t llqx latch enable low to output transition e = v il , g = v il min 0 0 0 ns ai03645 l e g a0-a18 dq0-dq31 valid tehlx tlhll tlhax tavll telll tlllh tehqx tehqz tghqx ghqz tllqx tllqv tglqx tglqv see also page read output
35/63 m58bw016bt, m58bw016bb, m58bw016dt, m58bw016db figure 11. asynchronous page read ac waveforms table 18. asynchronous page read ac characteristics note: for other timings see table 16, asynchronous bus read characteristics. symbol parameter test condition m58bw016 unit 80 90 100 t avqv1 address valid to output valid e = v il , g = v il max 25 25 25 ns t axqx address transition to output transition e = v il , g = v il min666ns ai03646 a0-a1 dq0-dq31 a0 and/or a1 tavqv1 output taxqx output + 1
m58bw016bt, m58bw016bb, m58bw016dt, m58bw016db 36/63 figure 12. asynchronous write ac waveform ai03651 dq0-dq31 w rp a0-a18 e = l g input valid valid twheh valid tavwh twlwh telwl input valid sr v pp twhax twhwl twhdx tdvwh twhgl twhqv tvphwh tqvvpl tqvpl tphwh rp = v dd rp = v hh read status register write cycle write cycle tavll
37/63 m58bw016bt, m58bw016bb, m58bw016dt, m58bw016db figure 13. asynchronous latch controlled write ac waveform ai03652 dq0-dq31 w rp a0-a18 l g input valid valid valid tavlh input valid sr v pp tlhax read status register write cycle write cycle e tlllh tllwh twhax telwl twlwh twheh twhwl twhgl twhqv tdvwh twhdx tvphwh tqvvpl tqvpl rp = v hh rp = v dd tavwh telll tavll
m58bw016bt, m58bw016bb, m58bw016dt, m58bw016db 38/63 table 19. asynchronous write and latch controlled write ac characteristics symbol parameter test condition m58bw016 unit 80 90 100 t avl l address valid to latch enable low min 0 0 0 ns t avw h address valid to write enable high e = v il min 50 50 50 ns t dvwh data input valid to write enable high e = v il min 50 50 50 ns t elll chip enable low to latch enable low min 0 0 0 ns t elwl chip enable low to write enable low min 0 0 0 ns t lhax latch enable high to address transition min 5 5 5 ns t lllh latch enable low to latch enable high min 10 10 10 ns t llwh latch enable low to write enable high e = v il min 50 50 50 ns t qvvpl output valid to v pp low min 0 0 0 ns t vphwh v pp high to write enable high min 0 0 0 ns t whax write enable high to address transition e = v il min 0 0 0 ns t whdx write enable high to input transition e = v il min 0 0 0 ns t wheh write enable high to chip enable high min 0 0 0 ns t whgl write enable high to output enable low min 150 150 150 ns t whqv write enable high to output valid min 175 175 175 ns t whwl write enable high to write enable low min 20 20 20 ns t wlwh write enable low to write enable high e = v il min 60 60 60 ns t qvpl output valid to reset/power-down low min 0 0 0 ns
39/63 m58bw016bt, m58bw016bb, m58bw016dt, m58bw016db figure 14. synchronous burst read (data valid from n clock rising edge) ai04409 dq0-dq31 a0-a18 l e g k valid tkhax n+2 n+1 n 1 0 tkhll tllkh telll tavll tkhlx tehqx tehqz tghqx tghqz tglqv setup output tkhqv tqvkh tavqv note : n depends on burst x-latency.
m58bw016bt, m58bw016bb, m58bw016dt, m58bw016db 40/63 table 20. synchronous burst read ac characteristics note: 1. data output should be read on the valid clock edge. 2. for other timings see table 16, asynchronous bus read characteristics. figure 15. synchronous burst read (data valid from n clock rising edge) note: for set up signals and timings see synchronous burst read. symbol parameter test condition m58bw016 unit 80 90 100 t avll address valid to latch enable low e = v il min 0 0 0 ns t bhkh burst address advance high to valid clock edge e = v il , g = v il , l = v ih min 8 8 8 ns t blkh burst address advance low to valid clock edge e = v il , g = v il , l = v ih min 8 8 8 ns t elll chip enable low to latch enable low min 0 0 0 ns t glqv output enable low to output valid e = v il , l = v ih min 25 25 25 ns t khax valid clock edge to address transition e = v il min 5 5 5 ns t khll valid clock edge to latch enable low e = v il min 0 0 0 ns t khlx valid clock edge to latch enable transition e = v il min 0 0 0 ns t khqx valid clock edge to output transition e = v il , g = v il , l = v ih min 3 3 3 ns t llkh latch enable low to valid clock edge e = v il min 6 6 6 ns t qvkh (1) output valid to valid clock edge e = v il , g = v il , l = v ih min 6 6 6 ns t rlkh valid data ready low to valid clock edge e = v il , g = v il , l = v ih min 6 6 6 ns t khqv valid clock edge to output valid e = v il , g = v il , l = v ih max 11 11 11 ns ai04408b k n+5 n+4 n+3 n+2 n+1 n dq0-dq31 tqvkh tkhqx q0 q1 q2 q3 q4 q5 setup burst read q0 to q3 tkhqv note: n depends on burst x-latency
41/63 m58bw016bt, m58bw016bb, m58bw016dt, m58bw016db figure 16. synchronous burst read - continuous - valid data ready output note: valid data ready = valid low during valid clock edge 1. v= valid output. 2. r is an open drain output with an internal pull up resistor of 1m w. the internal timing of r follows dq. an external resistor, typically 300k w. for a single memory on the r bus, should be used to give the data valid set up time required to recognize that valid data is available on the next valid clock edge. figure 17. synchronous burst read - burst address advance ai03649 k output (1) vvvv trlkh r v (2) ai03650 k add q0 q1 l q2 add valid g tglqv tblkh tbhkh b
m58bw016bt, m58bw016bb, m58bw016dt, m58bw016db 42/63 figure 18. reset, power-down and power-up ac waveform table 21. reset, power-down and power-up ac characteristics note: 1. this time is t phel + t avqv or t phel + t elqv . symbol parameter min max unit t phel reset/power-down high to chip enable low 50 ns t phqv (1) reset/power-down high to output valid 130 ns t phwl reset/power-down high to write enable low 50 ns t phgl reset/power-down high to output enable low 50 ns t plph reset/power-down low to reset/power-down high 100 ns t plrh reset/power-down low to valid data ready high 2 30 s t vdhph supply voltages high to reset/power-down high 10 s ai03849b w, rp tphwl tphel tphgl e, g vdd, vddq tvdhph tphwl tphel tphgl tplph tplrh power-up reset r
43/63 m58bw016bt, m58bw016bb, m58bw016dt, m58bw016db package mechanical figure 19. lbga80 10x12mm - 8x10 ball array, 1mm pitch, bottom view package outline note: drawing is not to scale. table 22. lbga80 10x12mm - 8x10 ball array, 1mm pitch, package mechanical data symbol millimeters inches typ min max typ min max a 1.700 0.0669 a1 0.400 0.350 0.450 0.0157 0.0138 0.0177 a2 1.100 0.0433 b 0.500 C C 0.0197 C C d 10.000 C C 0.3937 C C d1 7.000 C C 0.2756 C C ddd 0.150 0.0059 e 12.000 C C 0.4724 C C e1 9.000 C C 0.3543 C C e 1.000 C C 0.0394 C C fd 1.500 C C 0.0591 C C fe 1.500 C C 0.0591 C C sd 0.500 C C 0.0197 C C se 0.500 C C 0.0197 C C e1 e d1 d eb a2 a1 a bga-z05 ddd fd fe sd se e ball "a1"
m58bw016bt, m58bw016bb, m58bw016dt, m58bw016db 44/63 figure 20. pqfp80 - 80 lead plastic quad flat pack, package outline note: drawing is not to scale. table 23. pqfp80 - 80 lead plastic quad flat pack, package mechanical data symbol millimeters inches typ min max typ min max a 3.400 0.1339 a1 0.250 0.0098 a2 2.800 2.550 3.050 0.1102 0.1004 0.1201 b 0.300 0.450 0.0118 0.0177 c 0.130 0.230 0.0051 0.0091 d 23.200 22.950 23.450 0.9134 0.9035 0.9232 d1 20.000 19.900 20.100 0.7874 0.7835 0.7913 d2 18.400 C C 0.7244 C C e 0.800 C C 0.0315 C C e 17.200 16.950 17.450 0.6772 0.6673 0.6870 e1 14.000 13.900 14.100 0.5512 0.5472 0.5551 e2 12.000 C C 0.4724 C C l 0.800 0.650 0.950 0.0315 0.0256 0.0374 l1 1.600 C C 0.0630 C C a 0 7 0 7 n80 80 nd 24 24 ne 16 16 qfp-b d1 cp b e a2 a n l a1 a e1 e2 1 d c e d2 l1 nd ne
45/63 m58bw016bt, m58bw016bb, m58bw016dt, m58bw016db part numbering table 24. ordering information scheme note: devices are shipped from the factory with the memory content bits erased to 1. for a list of available options (speed, package, etc...) or for further information on any aspect of this de- vice, please contact the st sales office nearest to you. example: m58bw016b t 80 t 3 t device type m58 architecture b = burst mode operating voltage w = v dd = 2.7v to 3.6v; v ddq = v ddqin =2.4 to v dd device function 016b = 16 mbit (x32), boot block, burst tuning protection 016d = 16 mbit (x32), boot block, burst no tuning protection array matrix t = top boot b = bottom boot speed 80 = 80ns 90 = 90ns 100 = 100ns package t = pqfp80 za = lbga80: 1.0mm pitch temperature range 3 = C40 to 125 c 6 = C40 to 85 c option t = tape & reel packing
m58bw016bt, m58bw016bb, m58bw016dt, m58bw016db 46/63 appendix a. common flash interface - cfi the common flash interface is a jedec ap- proved, standardized data structure that can be read from the flash memory device. it allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the mem- ory. the system can interface easily with the de- vice, enabling the software to upgrade itself when necessary. when the cfi query command (rcfi) is issued the device enters cfi query mode and the data structure is read from the memory. tables 25, 26, 27, 28 and 29 show the addresses used to retrieve the data. table 25. query structure overview note: 1. offset 15h defines p which points to the primary algorithm extended query address table. 2. offset 19h defines a which points to the alternate algorithm extended query address table. table 26. cfi - query address and data output note: 1. the x8 or byte address and the x16 or word address mode are not available. 2. query data are always presented on dq7-dq0. dq31-dq8 are set to '0'. offset sub-section name description 00h manufacturer code 01h device code 10h cfi query identification string command set id and algorithm data offset 1bh system interface information device timing and voltage information 27h device geometry definition flash memory layout p(h) (1) primary algorithm-specific extended query table additional information specific to the primary algorithm (optional) a(h) (2) alternate algorithm-specific extended query table additional information specific to the alternate algorithm (optional) address a0-a18 data instruction 10h 51h "q" 51h; "q" query ascii string 52h; "r" 59h; "y" 11h 52h "r" 12h 59h "y" 13h 03h primary vendor: command set and control interface id code 14h 00h 15h 35h primary algorithm extended query address table: p(h) 16h 00h 17h 00h alternate vendor: command set and control interface id code 18h 00h 19h 00h alternate algorithm extended query address table 1ah 00h
47/63 m58bw016bt, m58bw016bb, m58bw016dt, m58bw016db table 27. cfi - device voltage and timing specification note: 1. bits are coded in binary code decimal, bit7 to bit4 are scaled in volts and bit3 to bit0 in mv. 2. bit7 to bit4 are coded in hexadecimal and scaled in volts while bit3 to bit0 are in binary code decimal and scaled in 100mv. 3. not supported. table 28. device geometry definition address a0-a18 data description 1bh 27h (1) v dd min, 2.7v 1ch 36h (1) v dd max, 3.6v 1dh b4h (2) v pp min 1eh c6h (2) v pp max 1fh 00h (3) 2 n ms typical time-out for word, dword prog C not available 20h 00h (3) 2 n ms, typical time-out for max buffer write C not available 21h 0ah 2 n ms, typical time-out for erase block 22h 00h (3) 2 n ms, typical time-out for chip erase C not available 23h 00h (3) 2 n x typical for word dword time-out max C not available 24h 00h 2 n x typical for buffer write time-out max C not available 25h 04h 2 n x typical for individual block erase time-out maximum 26h 00h (3) 2 n x typical for chip erase max time-out C not available address a0-a18 data description 27h 15h 2 n number of bytes memory size 28h 03h device interface sync./async. 29h 00h organization sync./async. 2ah 00h page size in bytes, 2 n 2bh 00h 2ch 02h bit7-0 = number of erase block regions in device 2dh 1eh number (n-1) of blocks of identical size; n=31 2eh 00h 2fh 00h erase block region information x 256 bytes per erase block (64kbytes) 30h 01h 31h 07h number (n-1) of blocks of identical size; n=8 32h 00h 33h 20h erase block region information x 256 bytes per erase block (8kbytes) 34h 00h
m58bw016bt, m58bw016bb, m58bw016dt, m58bw016db 48/63 table 29. extended query information note: 1. not supported. address offset address a18-a0 data (hex) description (p)h 35h 50h "p" query ascii string - extended table (p+1)h 36h 52h "r" (p+2)h 37h 49h "y" (p+3)h 38h 31h major version number (p+4)h 39h 31h minor version number (p+5)h 3ah 86h optional feature: (1=yes, 0=no) bit0, chip erase supported (0=no) bit1, suspend erase supported (1=yes) bit2, suspend program supported (1=yes) bit3, lock/unlock supported (1=yes) bit4, queue erase supported (0=no) bit 31-5 reserved for future use (p+6)h 3bh 01h optional features: synchronous read supported (p+7)h 3ch 00h (p+8)h 3dh 00h (p+9)h 3eh 01h function allowed after suspend: program allowed after erase suspend (1=yes) bit 7-1 reserved for future use (p+a)h 3fh 00h (1) block status register mask C not available
49/63 m58bw016bt, m58bw016bb, m58bw016dt, m58bw016db appendix b. flow charts figure 21. program flowchart and pseudo code note: 1. if an error is found, the status register must be cleared before further p/e operations. write 40h ai03850 start write address & data read status register yes no b7 = 1 yes no b3 = 0 no b4 = 0 v pp invalid error (1) program error (1) program command: C write 40h C write address & data (memory enters read status state after the program command) do: C read status register (e or g must be toggled) while b7 = 1 if b3 = 1, v pp invalid error: C error handler if b4 = 1, program error: C error handler yes end no b1 = 0 program to protect block error if b1 = 1, program to protected block error: C error handler yes
m58bw016bt, m58bw016bb, m58bw016dt, m58bw016db 50/63 figure 22. program suspend & resume flowchart and pseudo code write 70h ai00612 read status register yes no b7 = 1 yes no b2 = 1 program continues write ffh program/erase suspend command: C write b0h C write 70h do: C read status register while b7 = 1 if b4 = 0, program completed read memory array command: C write ffh C one or more data reads from other blocks write d0h program erase resume command: C write d0h to resume erasure C if the program operation completed then this is not necessary. the device returns to read array as normal (as if the program/erase suspend command was not issued). read data from another block start write b0h program complete write ffh read data
51/63 m58bw016bt, m58bw016bb, m58bw016dt, m58bw016db figure 23. block erase flowchart and pseudo code note: 1. if an error is found, the status register must be cleared before further p/e operations. write 20h ai03851 start write block address & d0h read status register yes no b7 = 1 yes no b3 = 0 yes b4 and b5 = 1 v pp invalid error (1) command sequence error erase command: C write 20h C write block address (a11-a18) & d0h (memory enters read status state after the erase command) do: C read status register (e or g must be toggled) if erase command given execute suspend erase loop while b7 = 1 if b3 = 1, v pp invalid error: C error handler if b4, b5 = 1, command sequence error: C error handler no no b5 = 0 erase error (1) yes no suspend suspend loop if b5 = 1, erase error: C error handler yes end yes no b1 = 0 erase to protected block error if b1 = 1, erase to protected block error: C error handler
m58bw016bt, m58bw016bb, m58bw016dt, m58bw016db 52/63 figure 24. erase suspend & resume flowchart and pseudo code write 70h ai00615 read status register yes no b7 = 1 yes no b6 = 1 erase continues write ffh program/erase suspend command: C write b0h C write 70h do: C read status register while b7 = 1 if b6 = 0, erase completed read memory array command: C write ffh C one or more data reads from other blocks write d0h read data from another block or program start write b0h erase complete write ffh read data program/erase resume command: C write d0h to resume the erase operation C if the program operation completed then this is not necessary. the device returns to read mode as normal (as if the program/erase suspend was not issued).
53/63 m58bw016bt, m58bw016bb, m58bw016dt, m58bw016db figure 25. unlock device and change tuning protection code flowchart ai04501 reset device locked by tuning code 1st: write cycle 2nd: write cycle (old code, factory setup = 0xffffh) yes 3rd: write cycle 4th: write cycle (old code, factory setup = 0xffffh) yes yes no device locked add: don't care data: 0x48h 6th: write cycle add: 0x00000h data: first 32 bit 7th: write cycle (new code) yes b7 = 1 add: don't care data: 0x48h 8th: write cycle add: 0x00001h data: second 32 bit 9th: write cycle (new code) yes b7 = 1 device unlocked reset device locked by new code tuning protection unlock sequence add: don't care data: 0xffh 5th: write cycle issue read command issue read command add: don't care data: 0x78h add: 0x00000h data: first 32 bit b7 = 1 add: don't care data: 0x78h add: 0x00001h data: second 32 bit b7 = 1 read status register b0 = 1 add: don't care data: 0xffh
m58bw016bt, m58bw016bb, m58bw016dt, m58bw016db 54/63 figure 26. unlock device and program a tuning protected block flowchart ai04502 reset device locked by tuning code add: don't care data: 0x78h 1st: write cycle add: 0x00000h data: first 32 bit 2nd: write cycle (first part of the tuning code) yes b7 = 1 add: don't care data: 0x78h 3rd: write cycle add: 0x00001h data: second 32 bit 4th: write cycle (second part of the tuning code) yes b7 = 1 yes no b0 = 1 device locked add: don't care data: 0x40h 6th: write cycle add: location to prog. data: data to prog. 7th: write cycle yes b7 = 1 device unlocked status register check location programmed tuning protection unlock sequence add: don't care data: 0xffh issue read command 5th: write cycle add: don't care data: 0xffh issue read command read status register
55/63 m58bw016bt, m58bw016bb, m58bw016dt, m58bw016db figure 27. unlock device and erase a tuning protected block flowchart ai04502 reset device locked by tuning code add: don't care data: 0x78h 1st: write cycle add: 0x00000h data: first 32 bit 2nd: write cycle (first part of the tuning code) yes b7 = 1 add: don't care data: 0x78h 3rd: write cycle add: 0x00001h data: second 32 bit 4th: write cycle (second part of the tuning code) yes b7 = 1 yes no b0 = 1 device locked add: don't care data: 0x20h 6th: write cycle add: block to erase data: 0xd0h 7th: write cycle yes b7 = 1 device unlocked status register check block erased tuning protection unlock sequence add: don't care data: 0xffh issue read command 5th: write cycle add: don't care data: 0xffh issue read command read status register
m58bw016bt, m58bw016bb, m58bw016dt, m58bw016db 56/63 figure 28. power-up sequence to burst the flash ai03834 power-up or reset asynchronous read write 60h command write 03h with a15-a0 bcr inputs synchronous read bcr bit 15 = '1' set burst configuration register command: C write 60h C write 03h and bcr on a15-a0 bcr bit 15 = '0' bcr bit 14-bit 0 = '1'
57/63 m58bw016bt, m58bw016bb, m58bw016dt, m58bw016db figure 29. command interface and program erase controller flowchart (a) ai03835 read elec. signature yes no 90h read status yes 70h no erase set-up yes 20h no program set-up yes 40h no clear status yes 50h no wait for command write read status read array yes d b c read cfi yes 98h no no d0h a erase command error e d
m58bw016bt, m58bw016bb, m58bw016dt, m58bw016db 58/63 figure 30. command interface and program erase controller flowchart (b) ai03836 tp program set_up yes no 48h set bcr set_up yes 60h no d tp unlock set_up yes 78h no ffh 03h no yes no e f g yes
59/63 m58bw016bt, m58bw016bb, m58bw016dt, m58bw016db figure 31. command interface and program erase controller flowchart (c) read status 70h b erase ready no a b0h no read status yes ready no erase suspend yes read array yes erase suspended read status yes no 40h no d0h no program set_up ai03837 yes yes no yes read status c
m58bw016bt, m58bw016bb, m58bw016dt, m58bw016db 60/63 figure 32. command interface and program erase controller flowchart (d) read status 70h b program ready no c b0h no read status yes ready no program suspend read array yes program suspended read status yes no no d0h ai03838 yes no yes read status yes
61/63 m58bw016bt, m58bw016bb, m58bw016dt, m58bw016db figure 33. command interface and program erase controller flowchart (e) b tp program ready f no read status ai03839 yes b tp unlock ready g no read status yes
m58bw016bt, m58bw016bb, m58bw016dt, m58bw016db 62/63 revision history table 30. document revision history date version revision details january-2001 -01 first issue. 05-jun-2001 -02 major rewrite and restructure. 15-jun-2001 -03 nd and ne values changed in pqfp80 package mechanical table 17-jul-2001 -04 pqfp80 package outline drawing and mechanical data table updated 17-dec-2001 -05 tlead removed from absolute maximum ratings (table 12) 80, 90 and 100ns speed classes defined (tables 16, 17, 18, 19 and 20 clarified accordingly) figures 14, 15, 16 and 17 clarified temperature range 3 and 6 added tables 13, 14, 15, 21 and cfi tables 26, 27, 28, 29 clarified document status changed from product preview to preliminary data 17-jan-2002 -06 dc characteristics i pp , i pp1 and i dd1 clarified ac bus read characteristics timing t ghqz clarified 30-aug-2002 6.1 revision numbering modified: a minor revision will be indicated by incrementing the tenths digit, and a major revision, by incrementing the units digit of the previous version (e.g. revision version 06 becomes 6.0). references of v pp pin used for block protection purposes removed. figure 9 modified. 4-sep-2002 7.0 datasheet status changed from preliminary data to full datasheet. t wlwh parameter modified in table 19, asynchronous write and latch controlled write ac characteristics. 13-may-2003 7.1 revision history moved to end of document. v pp clarified in program and block erase commands and status register, v pp status bit. v pplk added to dc characteristics table. timing t khqv modified.
63/63 m58bw016bt, m58bw016bb, m58bw016dt, m58bw016db information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners ? 2003 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malt a - morocco - singapore - spain - sweden - switzerland - united kingdom - united states www.st.com

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